Title
Formální postupy v diagnostice číslicových obvodů - verifikace testovatelného návrhu
Code
GA102/01/1531
Summary
The growing complexity of integrated circuits confronts the manufacturers with the problem of testability. The implementation of diagnostic principles has become an integral part of the process of digital circuit synthesis. During the synthesis the topic of testability are evaluated simultaneously with the synthesis - e. g. full scan, partial scan or BIST methods. Different aspects of the circuit design are evaluated and the controllability/observability of the inputs/outputs of internal elements of the unit under design is an important feature. The diagnostic methodologies utilized during the circuit synthesis are based on heuristic approaches during which the structure of the circuit is analysed. These heuristic approaches are different for different types of circuits. The goal of this project is the development of formal tools which can be used to represent diagnostic features of a circuit and its internal elements, based on theory of sets, theory of graphs and mathematical logic concepts.
Start year
2001
End year
2003
Provider
Grantová agentura ČR
Category
Obecná forma
Type
Standardní projekty
Solver
Information system of research, development and innovation (in Czech)